We're trying to do something like following in verilog: `define MY_SUFFIX suffix wire prefix_`MY_SUFFIX; assign prefix_`MY_SUFFIX = 1'b0;. ... <看更多>
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We're trying to do something like following in verilog: `define MY_SUFFIX suffix wire prefix_`MY_SUFFIX; assign prefix_`MY_SUFFIX = 1'b0;. ... <看更多>
... <看更多>
There are no operations permitted in `ifdef , but the code you wrote is fine. You can get the effect of OR or AND operations by additional ... ... <看更多>
verilog -modi-lookup: top_mac_ffsgpcs.v:596: Can't locate ``endif' module definition (Expanded macro to endif) ... <看更多>